Getting the PCIe of Avnet S6LX150T Development Kit detected
About a year ago, I had a client failing to get the PCIe working on an Avnet LX150T development board. Despite countless joint efforts, we failed to get the card detected as a PCIe device by the...
View ArticleLinux kernel hack for calming down a flood of PCIe AER messages
While working on a project involving a custom PCIe interface, Linux’ message log became flooded with messages like pcieport 0000:00:1c.6: device [8086:a116] error status/mask=00001081/00002000 pcieport...
View ArticleUsing Linux’ setpci to program an EEPROM attached to an PLX / Avago PCIe switch
Introduction These are my notes as I programmed an Atmel AT25128 EEPROM, attached to a PEX 8606 PCIe switch, using PCIe configuration-space writes only (that is, no I2C / SMBus cable). This is frankly...
View ArticleGigabit tranceivers on FPGA: Selected topics
Introduction This is a summary of a few topics that should to be kept in mind when a Multi-Gigabit Tranceiver (MGT) is employed in an FPGA design. It’s not a substitute for reading the relevant user...
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PCIe over fiber optics notes (using SFP+)
General As part of a larger project, I was required to set up a PCIe link between a host and some FPGAs through a fiber link, in order to ensure medical-grade electrical isolation of a high-bandwidth...
View ArticlePCIe: Xilinx’ pipe_clock module and its timing constraints
Introduction In several versions of Xilinx’ wrapper for the integrated PCIe block, it’s the user application logic’s duty to instantiate the module which generates the “pipe clock”. It typically looks...
View ArticlePCIe on Cyclone 10 GX: Data loss on DMA writes by FPGA
TL;DR DMA writes from a Cyclone 10 GX PCIe interface may be lost, probably due to a path that isn’t timed properly by the fitter. This has been observed with Quartus Prime Version 17.1.0 Build 240 SJ...
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Nvidia graphics cards on Linux: PCIe link speed and width
Why is it at 2.5 GT/s??? With all said about Nvidia’s refusal to release their drivers as open source, their Linux support is great. I don’t think I’ve ever had such a flawless graphics card experience...
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Intel FPGA’s Stratix 10: My impressions and notes
Introduction These are a few random things I wrote down as I worked with the Stratix 10 Development Kit, with focus on its PCIe interface. Quite obviously, it’s mostly about things I found noteworthy...
View ArticleCritical Warnings after upgrading a PCIe block for Ultrascale+ on Vivado 2020.1
Introduction Checking Xillybus’ bundle for Kintex Ultrascale+ on Vivado 2020.1, I got several critical warnings related to the PCIe block. As the bundle is intended to show how Xillybus’ IP core is...
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